Increasing energy consumption in data centers needs improvement with regard to power efficiencies. This requirement has triggered development of power topologies capable of direct power conversion from 48V to the point-of-load (PoL) voltage in numerous markets such as telecommunications, industrial, aerospace, and server environments. One attempted solution is transformer-based using a resonant/non-resonant half-bridge/full bridge plus a current doubler. Another attempted solution is the use of buck converters. Non-isolated buck converters have drawn the most attention for this application due to their inherent high efficiency and fast transient response. However, high step-down voltage conversion ratios imply a very low duty cycle, which difficult to implement in a single-stage buck converter. In order to overcome this problem, the industry is employing the emerging Gallium nitride (GaN) field-effect transistor technology capable of nanosecond switching times. Alternatively, cascaded buck converters are utilized, developing intermediate bus voltages and maintaining reasonable duty cycles achievable using silicon metal-oxide-semiconductor field-effect transistors (MOSFETs).
Both of the above-mentioned solutions suffer from a problem with a load release transient in the output voltage. Indeed, due to a very low output voltage, achievable current slew rate in the output filter inductor is low, i.e., −VO/L. Therefore, a very large access charge needs to be absorbed by the output capacitor, and a large output capacitor is required to prevent an overshoot of output voltage.
FIG. 1 depicts a prior-art cascaded buck converter receiving an input supply voltage VIN from an input source 101 and converting it to a low output voltage VO at a load 110. The cascaded converter includes an input buck converter stage including a first high-side switch 102, a first low-side switch 103, a first inductor 104, and an intermediate decoupling capacitor 105, an output buck converter stage including a second high-side switch 106, a second low-side switch 107, a second inductor 108, and an output decoupling capacitor 109. Intermediate decoupling capacitor 105 develops an intermediate bus voltage VC. First high-side switch 102 and first low-side switch 103 receive the gate drive signals G1 and G1. Second high-side switch 106 and second low-side switch 107 receive gate drive signals G2 and G2. First inductor 104 and second inductor 108 conduct currents I1 and I2 correspondingly. The output load 110 conducts output current IO.
FIG. 2 shows exemplary waveforms illustrating the prior art converter of FIG. 1 operated in constant on-time (COT) mode, without limiting the generality of the deficiencies it suffers in other control modes. Both buck converter stages are operated synchronously, and the waveforms 201 and 202 represent the gate drive signals G1 and G2 correspondingly.
The waveforms 203, 204, and 205 depict the currents I2, I1, and IO correspondingly. A step in the current 203 leaves residual energy in second inductor 108 that needs to be absorbed by output decoupling capacitor 109. As is depicted in FIG. 2, the converter of FIG. 1 is operated with small duty cycle, i.e., d=√{square root over (Vo/Vin)}<<1 and an intermediate bus voltage according to VC=√{square root over (VinVo)}. Accordingly, the down-slope slew rate dI2/dt=−VO/L2 is much slower than the rising slope dI2/dt=(VC−VO)/L2. Hence, the load release transient of the output current IO leaves an asymmetrically larger excess charge 207 in second inductor 108. This charge 207 causes a large overshoot of the output voltage VO seen in the waveform 206. The cascaded buck converters shown in FIGS. 1 and 2 operate at high step-down voltage ratios, resulting in an asymmetrically poor response to a load release transient.
Similar behavior causes an undershoot in the voltage 206 when the current 203 steps up. However, the issue is less severe due to the faster rising slope of the current 204.
Hence, a new power topology and a new control method are needed which are capable of a faster response to a load release transient for the 48V-to-PoL conversion.